View L9216A_1430516.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data sheet september 2001 L9216A/g short-loop ringing slic with ground start introduction the agere systems inc. l9216 is a subscriber line interface circuit (slic) that is optimized for short- loop, power-sensitive applications. this device pro- vides the complete set of line interface functionality, including power ringing needed to interface to a sub- scriber loop. this device has the capability to operate with a v cc supply of 3.3 v or 5 v and is designed to minimize external components required at all device interfaces. features n onboard ringing generation n three ringing input options: sine wave pwm logic level square wave n flexible v cc options: 5 v or 3.3 v v cc no C5 v required n battery switch to minimize off-hook power n eight operating states: scan mode for minimal power dissipation forward and reverse battery active on-hook transmission states ground start (tip open) ring mode disconnect mode n ultralow on-hook power: 27 mw scan mode 41 mw active mode n two slic gain options to minimal external compo- nents in codec interface n loop start, ring trip, and ground start detectors n software-controllable dual current-limit option n 28-pin plcc package n 48-pin mlcc package applications n voice over internet protocol (voip) n cable modems n terminal adapters (ta) n wireless local loop (wll) n telcordia technologies ? gr-909 access n network termination (nt) n key systems description this device is optimized to provide battery feed, ring- ing, and supervision on short-loop plain old tele- phone service (pots) loops. this device provides power ring to the subscriber loop through amplification of a low-voltage input. it provides forward and reverse battery feed states, on- hook transmission, a low-power scan state, ground start (tip open), and a forward disconnect state. the device requires a v cc and battery to operate. v cc may be either a 5 v or a 3.3 v supply. the ring- ing signal is derived from the high-voltage battery. a battery switch is included to allow for use of a lower- voltage battery in the off-hook mode, thus minimizing short-loop off-hook power. loop closure, ring trip, and ground start detectors are available. the loop closure detector has a fixed threshold with hysteresis. the ring trip detector requires a single-pole filter, thus minimizing external components required. the dc current limit is set and fixed by a logic control- lable pin. ground or open is applied to this pin set the current limit at the low or high value. the device is offered with two gain options. this allows for an optimized codec interface, with minimal external components regardless of whether a first- generation or a programmable third-generation codec is used.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 2 agere systems inc. table of contents contents page introduction..................................................................1 features ....................................................................1 applications...............................................................1 description ................................................................1 features ......................................................................4 description...................................................................4 architecture diagram...................................................7 pin information ............................................................8 operating states .......................................................10 state definitions ........................................................11 forward active ........................................................11 reverse active........................................................11 scan........................................................................11 on-hook transmissionforward battery ..............11 on-hook transmissionreverse battery ..............11 disconnect ..............................................................11 ring.........................................................................11 ground start ...........................................................11 thermal shutdown..................................................12 absolute maximum ratings (@ t a = 25 c) ..............12 electrical characteristics ...........................................13 test configurations ...................................................20 applications ...............................................................22 power control .........................................................22 dc loop current limit..............................................23 overhead voltage ...................................................23 active mode .........................................................23 scan mode ...........................................................23 on-hook transmission mode...............................23 ring mode............................................................24 loop range ............................................................24 battery reversal rate .............................................24 supervision................................................................24 loop closure...........................................................24 ring trip .................................................................24 tip or ring ground detector ...................................24 power ring .............................................................25 sine wave input signal and sine wave power ring signal output .................................26 pwm input signal and sine wave power ring signal output.............................................28 5 v v cc operation ................................................29 3.3 v v cc operation .............................................30 square wave input signal and trapezoidal power ring signal output .................................30 contents page ac applications ......................................................... 32 ac parameters........................................................ 32 codec types .......................................................... 32 first-generation codecs ..................................... 32 third-generation codecs .................................... 32 ac interface network .............................................. 32 design examples ................................................... 34 first-generation codec ac interface networkresistive termination ...................... 34 example 1, real termination .............................. 34 first-generation codec ac interface networkcomplex termination ....................... 37 complex termination impedance design example............................................................ 37 ac interface using first-generation codec ......... 37 transmit gain...................................................... 38 receive gain....................................................... 39 hybrid balance .................................................... 39 blocking capacitors ............................................ 40 third-generation codec ac interface networkcomplex termination ....................... 42 outline diagrams...................................................... 44 28-pin plcc .......................................................... 44 48-pin mlcc.......................................................... 45 48-pin mlcc, jedec mo-220 vkkd-2................ 46 ordering information ................................................ 47
preliminary data sheet september 2001 short-loop ringing slic w/ ground start L9216A/g agere systems inc. 3 table of contents (continued) figures page figure 1. architecture diagram ...................................7 figure 2. 28-pin plcc ...............................................8 figure 3. 48-pin mlcc................................................8 figure 4. basic test circuit ......................................20 figure 5. metallic psrr ...........................................21 figure 6. longitudinal psrr ....................................21 figure 7. longitudinal balance .................................21 figure 8. ac gains ....................................................21 figure 9. ringing waveform crest factor = 1.6 .......25 figure 10. ringing waveform crest factor = 1.2 .....25 figure 11. ring mode typical operation ..................26 figure 12. ring in operation ....................................27 figure 13. l9215/16 ringing input circuit selection table for square wave and pwm inputs .......................................................28 figure 14. modulation waveforms ............................29 figure 15. 5 v pwm signal amplitude .....................29 figure 16. ringing output on ring, with v cc = 5 v .................................................29 figure 17. 3.3 v pwm signal amplitude ..................30 figure 18. ringing output on ring, with v cc = 3.1 v ..............................................30 figure 19. square wave input signal and trapezoidal power ring signal output ...30 figure 20. crest factor vs. battery voltage .............31 figure 21. crest factor vs. r (k w ) ...........................31 figure 22. ac equivalent circuit ................................35 figure 23. agere t7504 first-generation codec resistive termination ..............................35 figure 24. interface circuit using first-generation codec (blocking capacitors not shown) ....................................................38 figure 25. ac interface using first-generation codec (including blocking capacitors) for complex termination impedance ...........40 figure 26. agere t7504 first-generation codec complex termination ..............................40 figure 27. third-generation codec ac interface network; complex termination ...............42 tables page table 1. pin descriptions .......................................... 9 table 2. control states ............................................. 10 table 3. supervision coding ................................... 10 table 4. recommended operating characteristics .......................................... 12 table 5. thermal characteristics.............................. 12 table 6. environmental characteristics .................... 13 table 7. 5 v supply currents ................................... 13 table 8. 5 v powering .............................................. 13 table 9. 3.3 v supply currents ............................... 14 table 10. 3.3 v powering ......................................... 14 table 11. 2-wire port .............................................. 15 table 12. analog pin characteristics ..................... 16 table 13. ac feed characteristics .......................... 17 table 14. logic inputs and outputs (v cc = 5 v) ..... 18 table 15. logic inputs and outputs (v cc = 3.3 v) .. 18 table 16. ground start ............................................ 18 table 17. ringing specifications ............................. 19 table 18. ring trip .................................................. 19 table 19. typical active mode on- to off-hook tip/ring current-limit transient response ................................................ 23 table 20. fb1 and fb2 values vs. typical ramp time ......................................................... 24 table 21. onset of power ringing clipping v cc = 5 v, cinput = 0.47 m f ................... 27 table 22. onset of power ringing clipping v cc = 3.1 v, cinput = 0.47 m f ................ 27 table 23. signal and component selection chart ... 28 table 24. parts list l9216; agere t7504 first- generation codec resistive termination; nonmeter pulse application ................... 36 table 25. parts list l9216; agere t7504 first- generation codec complex termination; meter pulse application ........................... 41 table 26. parts list l9216; agere t8536 third-generation codec ac and dc parameters; fully programmable ...... 43
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 4 agere systems inc. features n onboard balanced ringing generation: no ring relay no bulk ring generator required 15 hz to 70 hz ring frequency supported sine wave input-sine wave output pwm input-sine wave output square wave input-trapezoidal output n power supplies requirements: v cc talk battery and ringing battery required no C5 v supply required no high-voltage positive supply required n flexible vcc options: 5 v or 3.3 v v cc operation 5 v or 3.3 v v cc interchangeable and transparent to users n battery switch via logic control: minimize off-hook power dissipation n minimal external components required n eight operating states: forward active, v bat2 applied polarity reversal active, v bat2 applied on-hook transmission, v bat1 applied on-hook transmission polarity reversal, v bat1 applied ground start scan forward disconnect ring mode n unlatched parallel data control interface n ultralow slic power: scan 37 mw (v cc = 5 v) forward/reverse active 54 mw (v cc = 5 v) scan 27 mw (v cc = 3.3 v) forward/reverse active 41 mw (v cc = 3.3 v) n supervision: loop start, fixed threshold with hysteresis ring trip, single-pole ring trip filtering, fixed thresh- old as a function of battery voltage ring current for ground start applications, user- adjustable threshold n adjustable current limit: 25 ma or 40 ma via ground or open to control input n overhead voltage: clamped typically <51 v differentially clamped maximum <56.5 v single-ended n thermal shutdown protection with hysteresis n longitudinal balance: telcordia technologies gr-909 balance n ac interface: two slic gain options to minimize external com- ponents required for interface to first- or third-gen- eration codecs sufficient dynamic range for direct coupling to codec output n 28-pin plcc/48-pin mlcc package n 90 v cbic-s technology description the l9216 is designed to provide battery feed, ringing, and supervision functions on short plain old telephone service (pots) loops. this device is designed for ultralow power in all operating states. the l9216 offers eight operating states. the device assumes uses of a lower-voltage talk battery, a higher- voltage ringing battery, and a v cc supply. the l9216 requires only a positive v cc supply. no C5 v supply is needed. the l9216 can operate with a v cc of either 5 v or 3.3 v, allowing for greater user flex- ibility. the choice of v cc voltage is transparent to the user; the device will function with either supply voltage connected. two batteries are used: 1. a high-voltage ring battery (v bat1 ). v bat1 is a maximum C75 v. v bat1 is used for power ring signal amplification and for scan, on-hook transmission, and ground start modes. this supply is current limited to approximately the maximum power ringing current, typically 50 ma. 2. a lower-voltage talk battery (v bat2 ). v bat2 is used for active mode powering.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 5 description (continued) forward and reverse battery active modes are used for off-hook conditions. since this device is designed for short-loop applications, the lower-voltage v bat2 is applied during the forward and reverse active states . battery reversal is quiet, without breaking the ac path. rate of battery reversal may be ramped to control switching time. the magnitude of the overhead voltage in the forward and reverse active modes has a typical default value of 6.0 v, allowing for an undistorted signal of 3.14 dbm into 900 w . this overhead is fixed. the ring trip detec- tor is turned off during active modes to conserve power. because on-hook transmission is not allowed in the scan mode, an on-hook transmission mode is defined. this mode is functionally similar to the active mode, except the tip ring voltage is derived from the higher v bat1 rather than v bat2 . in the on-hook transmission modes with a primary battery whose magnitude is greater than a nominal 51 v, the magnitude of the tip to ground and ring to ground voltage is clamped at less than 56.5 v. to minimize on-hook power, a low-power scan mode is available. in this mode, all functions except off-hook supervision are turned off to conserve power. on-hook transmission is not allowed in the scan mode. in the scan mode with a primary battery whose magni- tude is greater than a nominal 51 v, the magnitude of the tip to ground and ring to ground voltage is clamped at less than 56.5 v. a forward disconnect mode is provided, where all cir- cuits are turned off and power is denied to the loop. the device offers a ring mode, in which a power ring signal is provided to the tip/ring pair. during the ring mode, a user-supplied low-voltage ring signal (ac-cou- pled) is input to the devices ring in input. this signal is amplified to produce the power ring signal. this signal may be a sine wave or filtered square wave to produce a sine wave on trapezoidal output. ring trip detector and common-mode current detector are active during the ring mode. this feature eliminates the need for a separate external ring relay, associated external circuitry, and a bulk ring- ing generator. see the applications section of this data sheet for more information. the device offers a ground start mode. in this mode, the tip drive amplifier is turned off. the device presents a high impedance (>100 k w ) to pt and a current-lim- ited battery (v bat1 ) to pr. v bat1 is clamped to less than 56.5 v in this mode as pr. a ring current detector for ring ground detection is included for ground start appli- cations. the threshold is user programmable via exter- nal resistors. see the applications section of this data sheet for more information on supervision functions. output pin rgdet indicates current flowing in the ring lead. both the ring trip and loop closure supervision func- tions are included. the loop closure has a fixed typical 10.5 ma on- to off-hook threshold in the active mode and a fixed 11.5 ma on- to off-hook threshold from the scan mode. in either case, there is a 2 ma hysteresis. the ring trip detector requires only a single-pole filter at the input, minimizing external components. the ring trip threshold at a given battery voltage is fixed. typical ring trip threshold is 42.5 ma for a C70 v v bat1. upon reaching the thermal shutdown temperature, the device will enter an all-off mode. upon cooling, the device will re-enter the state it was in prior to thermal shutdown. hysteresis is built in to prevent oscillation. longitudinal balance is consistent with north american gr-909 requirements. specifications are given in table 12. data control is via a parallel unlatched control scheme. the dc current limit is fixed to either 25 ma or 40 ma depending if ground or open is applied to the v prog current-limit programming pin. programming accuracy is 8%. circuitry is added to the l9216 to minimize the inrush of current from the v cc supply and to the battery supply during an on- to off-hook transition, thus saving in power supply design cost. see the applications section of this data sheet for more information. overhead in the active modes (v bat2 applied) is fixed to approximately 6.0 v is achieved. this is adequate for a 3.14 dbm overload into 900 w . transmit and receive gains have been chosen to mini- mize the number of external components required in the slic-codec ac interface, regardless of the choice of codec.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 6 agere systems inc. description (continued) the l9216 uses a voltage feed-current sense architec- ture; thus, the transmit gain is a transconductance. the l9216 transconductance is set via a single external resistor, and this device is designed for optimal perfor- mance with a transconductance set at 300 v/a. the l9216 offers an option for a single-ended to differ- ential receive gain of either 8 or 2. these options are mask programmable at the factory and are selected by choice of code. a receive gain of 8 is more appropriate when choosing a first-generation type codec where termination imped- ance, hybrid balance, and overall gains are set by external analog filters. the higher gain is typically required for synthesization of complex termination impedance. a receive gain of 2 is more appropriate when choosing a third-generation type codec. third-generation codecs will synthesize termination impedance and set hybrid balance and overall gains. to accomplish these func- tions, third-generation codecs typically have both ana- log and digital gain filters. for optimal signal to noise performance, it is best to operate the codec at a higher gain level. if the slic then provides a high gain, the slic output may be saturated causing clipping distor- tion of the signal at tip and ring. to avoid this situation, with a higher gain slic, external resistor dividers are used. these external components are not necessary with the lower gain offered by the l9216. see the appli- cations section of this data sheet for more information. the l9216 is internally referenced to 1.5 v. this refer- ence voltage is output at the v ref output of the device. the slic output vitr is also referenced to 1.5 v; therefore, it must be ac coupled to the codec input. however, the slic inputs rcvp/rcvn are floating inputs. if there is not feedback from rcvp/rcvn to vitr, rcvp/rcvn may be directly coupled to the codec output. if there is feedback from rcvp/rcvn to vitr, rcvp/rcvn must be ac coupled to the codec output. the l9216 is packaged in a 28-pin plcc package and an ultrasmall 48-pin mlcc package. use L9216A for gain of eight applications and l9216g for gain of two applications.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 7 architecture diagram 12-3530.e (f) figure 1. architecture diagram v ref vitr txi itr vtx pt pr icm rgdet cf2 cf1 fb2 fb1 power agnd v cc bgnd v bat2 v bat1 v prog nstat rtflt dcout 1.5 v band-gap reference aac b = 20 out (itr/306) tip/ring current sense +1 itr itr rft 18 w rfr 18 w v reg C1 v reg ringing 27.5x parallel data interface ring in b0 b1 b2 x1 x1 rcvn rcvp current limit and inrush control ring loop rectifier vtx common- mode current detector trip closure v ref C + 9216a gain = 4 + C + C C + gain ax 9216g gain = 1 ac interface
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 8 agere systems inc. pin information 12-3558.d (f) figure 2. 28-pin plcc figure 3. 48-pin mlcc b0 b1 b2 pr pt fb1 dcout cf2 cf1 rtflt 5 6 7 8 9 10 11 4212827 3 12 14 15 16 17 18 13 25 24 23 22 21 20 19 nstat v bat2 agnd icm rgdet v bat1 v cc bgnd v prog ring in v ref fb2 vtx txi vitr rcvp rcvn 26 itr l9216 pr 28-pin plcc 1 3 4 6 7 8 9 10 11 12 2 48 46 45 44 43 42 41 40 38 37 47 13 16 17 18 19 20 21 22 23 24 14 36 33 32 31 30 29 28 27 26 25 35 b2 pt fb1 agnd ring in pr rcvn nstat rcvp txi itr fb2 bgnd v ref v bat2 vitr 34 vtx 39 15 5 dcout cf2 cf1 rtflt v cc v bat1 icm b1 b0 35 L9216A/g 48-pin mlcc rgdet nc nc nc nc v prog nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 9 pin information (continued) table 1. pin descriptions 28-pin plcc 48-pin mlcc symbol type name/function 143nstato loop closure detector outputring trip detector output. when low, this logic output indicates that an off-hook condition exists or ringing is tripped. 245vitro transmit ac output voltage. output of internal aac amplifier. this output is a voltage that is directly proportional to the differen- tial ac tip/ring current. 3 47 rcvp i receive ac signal input (noninverting). this high-impedance input controls the ac differential voltage on tip and ring. this node is a floating input. 448rcvni receive ac signal input (inverting). this high-impedance input controls the ac differential voltage on tip and ring. this node is a floating input. 51ring in i power ring signal input. ac-couple to a sine wave or lower crest factor low-voltage ring signal. the input here is amplified to pro- vide the full power ring signal at tip and ring. this signal may be applied continuously, even during nonringing states. 66dcouto dc output voltage. this output is a voltage that is directly propor- tional to the absolute value of the differential tip/ring current. this is used to set ring trip threshold. 77v prog i current-limit program input. connect ground to this pin to set current-limit to 25 ma, float to this pin to set current limit to 40 ma. 89cf2 filter capacitor. connect a capacitor from this node to ground. 910cf1 filter capacitor. connect a capacitor from this node to cf2. 10 12 rtflt ring trip filter. connect this lead to dcout via a resistor and to agnd with a capacitor to filter the ring trip circuit to prevent spuri- ous responses. a single-pole filter is needed. 11 13 v ref o slic internal reference voltage. output of internal 1.5 v refer- ence voltage. 12 15 agnd gnd analog signal ground. 13 16 v cc pwr analog power supply. user choice of 5 v or 3.3 v nominal power or supply. 14 19 v bat1 pwr battery supply 1. high-voltage battery. 15 20 v bat2 pwr battery supply 2. lower-voltage battery. 16 22 bgnd gnd battery ground. ground return for the battery supplies. 2, 3, 4, 5, 8, 11, 14, 17, 18, 21, 27, 28, 30, 32, 36, 37, 39, 42, 44, 46 nc no connection. 17 23 rgdet o ring ground detect. when high, this open collector output indi- cates the presence of a ring ground or a tip ground. this supervi- sion output may be used in ground key, ground start or common- mode fault detection applications. 18 24 icm i common-mode current sense. to program tip or ring ground sense threshold, connect a resistor to v cc and connect a capacitor to agnd to filter 50/60 hz. if unused, the pin is connected to ground.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 10 agere systems inc. pin information (continued) table 1. pin descriptions (continued) operating states table 2. control states table 3. supervision coding 28-pin plcc 48-pin mlcc symbol type name/function 19 25 fb2 polarity reversal slowdown capacitor. connect a capacitor from this node to ground for controlling rate of battery reversal. if ramped battery reversal is not desired, this pin is left open. 20 26 fb1 polarity reversal slowdown capacitor. connect a capacitor from this node to ground for controlling rate of battery reversal. if ramped battery reversal is not desired, this pin is left open. 21 29 pt i/o protected tip. the output drive of the tip amplifier and input to the loop sensing circuit. connect to loop through overvoltage and overcur- rent protection. 22 31 pr i/o protected ring. the output drive of the ring amplifier and input to the loop sensing circuit. connect to loop through overvoltage and overcur- rent protection. 23 33 b2 i d state control input. these pins have an internal 110 k w pull-down. 24 34 b1 i d 25 35 b0 i d 26 38 itr i transmit gain. input to ax amplifier. connect a 4.75 k w resistor from this node to vtx to set transmit gain. gain shaping for termination impedance with a first-generation codec is also achieved with a net- work from this node to vtx. 27 40 vtx o ac output voltage. output of internal ax amplifier. the voltage at this pin is directly proportional to the differential tip/ring current. 28 41 txi i ac/dc separation. input to internal aac amplifier. connect a 0.1 m f capacitor from this pin to vtx. b0 b1 b2 state 1 1 0 forward active 1 0 0 reverse active 1 1 1 on-hook transmission forward battery 1 0 1 on-hook transmission reverse battery 0 0 1 ground start 01 1scan 0 0 0 disconnect, device will power up in this state 01 0ring nstat rgdet 0 = off-hook or ring trip or tsd. 1 = on-hook and no ring trip and no tsd or disconnect state. 0 = no ring or tip ground. 1 = ring or tip ground.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 11 state definitions forward active n pin pt is positive with respect to pr. n v bat2 is applied to tip/ring drive amplifiers. n loop closure and common-mode detect are active. n ring trip detector is turned off to conserve power. n overhead is set to nominal 6.0 v for undistorted transmission of 3.14 dbm into 900 w . reverse active n pin pr is positive with respect to pt. n v bat2 is applied to tip/ring drive amplifiers. n loop closure and common-mode detect are active. n ring trip detector is turned off to conserve power. n overhead is set to nominal 6.0 v for undistorted transmission of 3.14 dbm into 900 w . scan n except for loop closure, all circuits (including ring trip and common-mode detector) are powered down. n on-hook transmission is disabled. n pin pt is positive with respect to pr, and v bat1 is applied to tip/ring. n the tip to ring on-hook differential voltage will be typ- icallybetween C44 v and C51 v with a C70 v primary battery. on-hook transmission forward battery n pin pt is positive with respect to pr. n v bat1 is applied to tip/ring drive amplifiers. n supervision circuits, loop closure, and common- mode detect are active. n ring trip detector is turned off to conserve power. n on-hook transmission is allowed. n the tip-to-ring on-hook differential voltage will be typ- ically between C41 v and C49 v with a C70 v primary battery. on-hook transmission reverse battery n pin pr is positive with respect to pt. n v bat1 is applied to tip/ring drive amplifiers. n supervision circuits, loop closure, and common- mode detect are active. n ring trip detector is turned off to conserve power. n on-hook transmission is allowed. n the tip-to-ring on-hook differential voltage will be typ- ically between C41 v and C49 v with a C70 v primary battery. disconnect n the tip/ring amplifiers and all supervision are turned off. n the slic goes into a high-impedance state. n nstat is forced high (on-hook). n device will power up in this state. ring n power ring signal is applied to tip and ring. n input waveform at ring in is amplified. n ring trip supervision and common-mode current supervision are active; loop closure is inactive. n overhead voltage is reduced to typically 4 v. n current is limited by saturation current of the amplifi- ers themselves, typically 100 ma at 125 c. ground start n tip drive amplifer is turned off. n device presents a high impedance (>100 k w ) to pin pt. n device presents a clamped (<56.5 v) current-limited battery (v bat1 ) to pr. n output pin rgdet indicates current flowing in the ring lead. thermal shutdown n not controlled via truth table inputs. n nstat is forced low (off-hook) during this state. n this mode is caused by excessive heating of the device, such as may be encountered in an extended power cross situation.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 12 agere systems inc. absolute maximum ratings (@ t a = 25 c) stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. note: the ic can be damaged unless all ground connections are applied before, and removed after, all other connections. furtherm ore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. for example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage. table 4. recommended operating characteristics table 5. thermal characteristics 1. this parameter is not tested in production. it is guaranteed by design and device characterization. 2. airflow, pcb board layers, and other factors can greatly affect this parameter. parameter symbol min typ max unit dc supply (v cc ) C0.5 7.0 v battery supply (v bat1 ) C80v battery supply (v bat2 ) v bat1 v logic input voltage C0.5 v cc + 0.5 v logic output voltage C0.5 v cc + 0.5 v operating temperature range C40 125 c storage temperature range C40 150 c relative humidity range 5 95 % pt or pr fault voltage (dc) v pt , v pr v bat C 5 3 v pt or pr fault voltage (10 x 1000 m s) v pt , v pr v bat C 15 15 v ground potential difference (bgnd to agnd) 1 v parameter min typ max unit 5 v dc supplies (v cc )5.05.25v 3 v dc supplies (v cc )3.133.3v high office battery supply (v bat1 ) C60 C70 C75 v auxiliary office battery supply (v bat2 ) C12 v bat1 v operating temperature range C40 25 85 c parameter min typ max unit thermal protection shutdown (t jc ) 1 150 165 c 28-pin plcc thermal resistance junction to ambient ( q ja ) 2 : natural convection 2s2p board natural convection 2s0p board wind tunnel 100 linear feet per minute (lfpm) 2s2p board wind tunnel 100 linear feet per minute (lfpm) 2s0p board 35.5 50.5 31.5 42.5 c/w c/w c/w c/w 48-pin mlcc thermal resistance junction to ambient ( q ja ) 1, 2 38 c/w
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 13 electrical characteristics table 6. environmental characteristics 1. not to exceed 26 grams of water per kilogram of dry air. table 7. 5 v supply currents v bat1 = C70 v, v bat2 = C21 v, v cc = 5 v. table 8. 5 v powering v bat1 = C70 v, v bat2 = C21 v, v cc = 5 v. parameter min typ max unit temperature range C40 85 c humidity range 1 595 1 %rh parameter min typ max unit supply currents (scan state; no loop current): i vcc i vbat1 i vbat2 4.30 0.24 3 4.80 0.35 6 ma ma m a supply currents (forward/reverse active; no loop current, with or without ppm, v bat2 applied): i vcc i vbat1 i vbat2 5.95 25 1.2 7.0 85 1.40 ma m a ma supply currents (on-hook transmission mode; no loop current, with or without ppm, v bat1 applied): i vcc i vbat1 i vbat2 6.0 1.5 1.5 7.0 1.9 6 ma ma m a supply currents (disconnect mode): i vcc i vbat1 i vbat2 2.7 15 3.5 3.75 110 25 ma m a m a supply currents (ground start mode, no loop current): i vcc i vbat1 i vbat2 4.0 0.24 2 ma ma m a supply currents (ring mode; no load): i vcc i vbat1 i vbat2 5.9 1.8 2 6.5 2.2 6 ma ma m a parameter min typ max unit power dissipation (scan state; no loop current) 38 46 mw power dissipation (forward/reverse active; no loop current, v bat2 applied) 57 64 mw power dissipation (on-hook transmission mode; no loop current, v bat1 applied) 135 165 mw power dissipation (disconnect mode) 14 23 mw power dissipation (ground start mode) 37 mw power dissipation (ring mode; no load) 156 184 mw
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 14 agere systems inc. electrical characteristics (continued) table 9. 3.3 v supply currents v bat1 = C70 v, v bat2 = C21 v, v cc = 3.3 v. table 10. 3.3 v powering v bat1 = C70 v, v bat2 = C21 v, v cc = 3.3 v. parameter min typ max unit supply currents (scan state; no loop current): i vcc i vbat1 i vbat2 3.2 0.24 3 3.6 0.35 6 ma ma m a supply currents (forward/reverse active; no loop current, v bat2 applied): i vcc i vbat1 i vbat2 4.8 25 1.2 5.7 85 1.4 ma m a ma supply currents (on-hook transmission mode; no loop current, v bat1 applied): i vcc i vbat1 i vbat2 4.9 1.5 1.5 5.7 1.9 6 ma ma m a supply currents (disconnect mode): i vcc i vbat1 i vbat2 1.8 8 2 2.5 110 25 ma m a m a supply currents (ground start mode, no loop current): i vcc i vbat1 i vbat2 3.1 0.24 2 ma ma m a supply currents (ring mode; no load): i vcc i vbat1 i vbat2 4.70 1.8 2 5.4 2.2 6 ma ma m a parameter min typ max unit power dissipation (scan state; no loop current) 27 36.5 mw power dissipation (forward/reverse active; no loop current, v bat2 applied) 42 53 mw power dissipation (on-hook transmission mode; no loop current, v bat1 applied) 121 151 mw power dissipation (disconnect mode) 6.5 15 mw power dissipation (ground start mode) 27 mw power dissipation (ring mode; no loop current) 141 172 mw
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 15 electrical characteristics (continued) table 11. 2-wire port parameter min typ max unit tip or ring drive current = dc + longitudinal + signal currents 105 map tip or ring drive current = ringing + longitudinal 65 map signal current 10 marms longitudinal current capability per wire (longitudinal current is indepen- dent of dc loop current.) 8.5 15 marms ringing current (r load = 1386 w + 40 m f) 29 marms ringing current limit (r load = 100 w )50map dc loop currenti lim (v bat2 applied, r loop = 100 w ): v prog = 0 v prog = open 25 40 ma ma dc current variation 8 % dc feed resistance (does not include protection resistors) 50 w open loop voltages: scan mode: |v bat1 | > 51 v |v tip | C |v ring | pr to battery ground pt to battery ground oht mode: |v bat1 | > 51 v |v tip | C |v ring | pr to battery ground pt to battery ground active mode: |pt C pr| C |v bat2 | ring mode: |pt C pr| C |v bat1 | 44 41 5.75 51 49 6.25 4 56.5 56.5 56.5 56.5 6.75 v v v v v v v v
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 16 agere systems inc. electrical characteristics (continued) table 11. 2-wire port (continued) table 12. analog pin characteristics parameter min typ max unit loop closure threshold: active/on-hook transmission modes scan mode 10.5 11.5 ma ma loop closure threshold hysteresis: v cc = 5 v active mode v cc = 3.3 v active mode v cc = 5 v ground start mode v cc = 3.3 v ground start mode 2 1 6 5 ma ma ma ma longitudinal to metallic balance at pt/pr test method: q552 (11/96) section 2.1.2 and ieee ? 455: 300 hz to 600 hz 600 hz to 3.4 khz 52 52 db db metallic to longitudinal (harm) balance: 200 hz to 1000 hz 100 hz to 4000 hz 40 40 db db psrr 500 hz3000 hz: v bat1 , v bat2 v cc (5 v operation) 45 35 db db parameter min typ max unit txi (input impedance) 100 k w output offset (vtx) output offset (vitr) output drive current (vtx) output drive current (vitr) output voltage swing: maximum (vtx, vitr) minimum (vtx) minimum (vitr) output short-circuit current output load resistance output load capacitance 300 10 agnd agnd + 0.25 agnd + 0.35 10 20 10 100 v cc v cc C 0.5 v cc C 0.4 50 mv mv m a m a v v v ma k w pf rcvn and rcvp: input voltage range (v cc = 5 v) input voltage range (v cc = 3.3 v) input bias current 0 0 0.05 v cc C 0.5 v cc C 0.3 v v m a differential pt/pr current sense (dcout): gain (pt/pr to dcout) offset voltage at i loop = 0 C20 67 20 v/a mv
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 17 electrical characteristics (continued) table 13. ac feed characteristics 1. set externally either by discrete external components or a third- or fourth-generation codec. any complex impedance r1 + r2 | | c between 150 w and 1400 w can be synthesized. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. 3. vitr transconductance depends on the resistor from itr to vtx. this gain assumes an ideal 4750 w , the recommended value. positive cur- rent is defined as the differential current flowing from pt to pr. parameter min typ max unit ac termination impedance 1 150 600 1400 w total harmonic distortion (200 hz 4 khz) 2 : off-hook on-hook 0.3 1.0 % % transmit gain (f = 1004 hz, 1020 hz, current limit) 3 : pt/pr current to vitr 300 C 3% 300 300 + 3% v/a receive gain, f = 1004 hz, 1020 hz open loop: rcvp or rcvn to ptpr (gain of 8 option, L9216A) rcvp or rcvn to ptpr (gain of 2 option, l9216g) 7.76 1.94 8 2 8.24 2.06 gain vs. frequency (transmit and receive) 2 600 w termination, 1004 hz, 1020 hz reference: 200 hz300 hz 300 hz3.4 khz 3.4 khz20 khz 20 khz266 khz C0.3 C0.05 C3.0 0 0 0 0.05 0.05 0.05 2.0 db db db db gain vs. level (transmit and receive) 2 0 dbv reference: C55 db to +3.0 db C0.05 0 0.05 db idle-channel noise (tip/ring) 600 w termination: psophometric c-message 3 khz flat C82 8 C77 13 20 dbmp dbrnc dbrn idle-channel noise (vtx) 600 w termination: psophometric c-message 3 khz flat C82 8 C77 13 20 dbmp dbrnc dbrn
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 18 agere systems inc. electrical characteristics (continued) table 14. logic inputs and outputs (v cc = 5 v) table 15. logic inputs and outputs (v cc = 3.3 v) table 16. ground start parameter symbol min typ max unit input voltages: low level high level v il v ih C0.5 2.0 0.4 2.4 0.7 v cc v v input current: low level (v cc = 5.25 v, v i = 0.4 v) high level (v cc = 5.25 v, v i = 2.4 v) i il i ih 50 50 m a m a output voltages (open collector with internal pull-up resistor): low level (v cc = 4.75 v, i ol = 200 m a) high level (v cc = 4.75 v, i oh = C20 m a) v ol v oh 0 2.4 0.2 0.4 v cc v v parameter symbol min typ max unit input voltages: low level high level v il v ih C0.5 2.0 0.2 2.5 0.5 v cc v v input current: low level (v cc = 3.46 v, v i = 0.4 v) high level (v cc = 3.46 v, v i = 2.4 v) i il i ih 50 50 m a m a output voltages (open collector with internal 60 k w pull-up resistor): low level (v cc = 3.13 v, i ol = 200 m a) high level (v cc = 3.13 v, i oh = C5 m a) v ol v oh 0 2.2 0.2 0.5 v cc v v parameter min typ max unit tip open mode: tip input impedance 150 k w detector accuracy 20 % detection 50 ms
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 19 electrical characteristics (continued) table 17. ringing specifications table 18. ring trip ringing will not be tripped by the following loads: n 10 k w resistor in parallel with a 6 f capacitor applied across tip and ring. ring frequency = 17 hz to 23 hz. n 100 w resistor in series with a 2 f capacitor applied across tip and ring. ring frequency = 17 hz to 23 hz. parameter min typ max unit ring in (this input is ac coupled through 0.47 f.): input voltage swing input impedance 0 100 v cc v k w ring signal isolation: pt/pr to vitr ring mode 60 db ring signal isolation: ring in to pt/pr nonring mode 80 db ringing voltage (5 ren 1380 w + 40 f load, 100 w loop, 2 x 50 w protection resistors, C70 v battery) 40 vrms ringing voltage (3 ren 2310 w + 24 f load, 250 w loop, 2 x 50 w protection resistors, C70 v battery) 40 vrms ring signal distortion: 5 ren 1380 w , 40 f load, 100 w loop 3 ren 2310 w , 24 f load, 250 w loop 3 3 % % differential gain: ring in to pt/prno load 55 parameter min typ max unit ring trip (nstat = 0): loop resistance (total) high battery 100 600 w ring trip (nstat = 1): loop resistance (total) high battery 10 k w trip time (f = 20 hz) 100 ms
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 20 agere systems inc. test configurations 12-3531.h (f) figure 4. basic test circuit v bat2 v bat1 bgnd v cc agnd icm rgdet 0.1 m f 0.1 m f 0.1 m f rtflt dcout pr pt v prog v ref 0.1 m f 383 k w 30 w 30 w cf1 cf2 b0 b1 b2 0.1 m f ring in vitr rcvp rcvn itr vtx txi v bat2 v bat1 v cc 0.47 m f r loop 100 w /600 w tip ring fb2 fb1 0.1 m f l9216 nstat b0 b1 b2 4750 w 0.1 m f vitr rcv ring in 114 k w 0.1 m f 60.4 k w 0.1 m f 26.7 k w 69.8 k w rcv v cc basic test circuit
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 21 test configurations (continued) 12-2582.c (f) figure 5. metallic psrr 12-2583.b (f) figure 6. longitudinal psrr 12-2584.c (f) figure 7. longitudinal balance 12-2587.g (f) figure 8. ac gains v s 4.7 m f 100 w v bat or v cc disconnect v t/r v bat or v cc tip ring basic test circuit + C psrr = 20log v s v t/r 600 w bypass capacitor v s 4.7 m f 100 w v bat or v cc disconnect bypass capacitor 56.3 w v bat or v cc tip ring basic test circuit psrr = 20log v s v m 67.5 w 10 m f 10 m f 67.5 w v m + C tip ring basic test circuit longitudinal balance = 20log v s v m 368 w 100 m f 100 m f 368 w v m + C v s pt pr basic test circuit 600 w v t/r + C g xmt = v xmt v t/r g rcv = v t/r v rcv rcv v s vitr rcv
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 22 agere systems inc. applications power control under normal device operating conditions, power dissi- pation on the device must be controlled to prevent the device temperature from rising above the thermal shut- down and causing the device to shut down. power dis- sipation is highest with higher battery voltages, higher current limit, and under shorter dc loop conditions. additionally, higher ambient temperature will also reduce thermal margin. to support required power ringing voltages, this device is meant to operate with a high-voltage primary battery (C65 v to C75 v typically). thus, power control is nor- mally achieved by use of the battery switch and an aux- iliary lower absolute voltage battery. operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop length and protection resistor values, airflow, and number of pc board layers will influence the overall thermal performance. the fol- lowing example illustrates typical thermal design con- siderations. the thermal resistance of the 28-pin plcc package is typically 35.5 c/w, which is representative of the natu- ral airflow as seen in a typical switch cabinet with a multilayer board. the l9216 will enter thermal shutdown at a tempera- ture of 150 c. the thermal design should ensure that the slic does not reach this temperature under normal operating conditions. for this example, assume a maximum ambient operat- ing temperature of 85 c, a maximum current limit of 30 ma, a maximum battery of C75 v, and an auxiliary battery of C21 v. assume a (worst-case) minimum dc loop of 20 w of wire resistance, 30 w protection resis- tors, and 200 w for the handset. additionally, include the effects of parameter tolerance. 1. t tsd C t ambient(max) = allowed thermal rise. 150 c C 85 c = 65 c. 2. allowed thermal rise = package thermal impedance ? slic power dissipation. 65 c = 35.5 c/w ? slic power dissipation slic power dissipation (p d ) = 1.83 w. thus, if the total power dissipated in the slic is less than 1.83 w, it will not enter the thermal shutdown state. total slic power is calculated as: to ta l p d = maximum battery ? maximum current limit + slic quiescent power. for the l9216, the worst-case slic on-hook active power is 75 mw. thus, total off-hook power = (i loop )(current-limit tolerance)*(v batapplied ) + slic on-hook power total off-hook power = (0.030 a)(1.08) * (21) + 75 mw total off-hook power = 755.4 mw the power dissipated in the slic is the total power dis- sipation less the power that is dissipated in the loop. slic p d = total power C loop power loop off-hook power = (i loop * 1.08) 2 ? (r loop(dc) min + 2r handset ) loop off-hook power = (0.030 a)(1.08) 2 ? (20 w + 60 w + 200 w ) loop off-hook power = 293.9 mw slic off-hook power = total off-hook power C loop off-hook power slic off-hook power = 755.4 mw C 293.9 mw slic off-hook power = 461.5 mw < 1.83 w thus, under the operating conditions of this example, the thermal design, using the auxiliary, is adequate to ensure the device is not driven into thermal shutdown under worst-case operating conditions.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 23 applications (continued) dc loop current limit current limit may be chosen from two discrete values, 25 ma or 40 ma, depending on if v prog is grounded (25 ma) or left floating (40 ma). note that there is a 12.5 k w slope to the i/v characteristic in the current- limit region; thus, once in current limit, the actual loop current will increase slightly, as loop length decreases. the above describes the active mode steady-state cur- rent-limit response. there will be a transient response of the current-limit circuit upon an on- to off-hook transi- tion. typical active mode transient current-limit response is given in table 19. table 19. typical active mode on- to off-hook tip/ ring current-limit transient response overhead voltage active mode overhead is fixed to a nominal 6.0 v, which is adequate for on-hook transmission of 3.14 dbm into 900 w . scan mode if the magnitude of the primary battery is greater than 51 v, the magnitude of the open loop tip-to-ring open loop voltage is clamped typically between 44 v and 51 v. if the magnitude of the primary battery is less than a nominal 51 v, the overhead voltage will track the magnitude of the battery voltage, i.e., the magnitude of the open circuit tip-to-ring voltage will be 4 v to 6 v less than battery. in the scan mode, overhead is unaffected by v ovh . on hook transmission mode if the magnitude of the primary battery is greater than 51 v, the magnitude of the open loop tip-to-ring open loop voltage is clamped typically between 41 v and 49 v. if the magnitude of the primary battery is less than a nominal 51 v, the overhead voltage will track the magnitude of the battery voltage, i.e., the magnitude of the open circuit tip-to-ring voltage will be 6 v to 8 v less than battery. in the scan mode, overhead is unaffected by v ovh . parameter value unit dc loop current: active mode r loop = 100 w on- to off-hook transition t < 5 ms i lim + 60 ma dc loop current: active mode r loop = 100 w on- to off-hook transition t < 50 ms i lim + 20 ma dc loop current: active mode r loop = 100 w on- to off-hook transition t < 300 ms i lim ma
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 24 agere systems inc. applications (continued) overhead voltage (continued) ring mode in the ring mode, to maximize ringing loop length, the overhead is decreased to the saturation of the tip ring drive amplifiers, a nominal 4 v. the tip to ground volt- age is 1 v, and the ring to v bat1 voltage is 3 v. during the ring mode, to conserve power, the receive input at rcvn/rcvp is deactivated. during the ring mode, to conserve power, the aac amplifier in the transmit direction at vitr is deactivated. however, if the ax amplifier at vtx is active during the ring mode, differential ring current may be sensed at vtx during the ring mode. loop range the dc loop range is calculated using: r l = C 2r p C r dc v bat2 is typically applied under off-hook conditions for power conservation and slic thermal considerations. the l9216 is intended for short-loop applications and, therefore, will always be in current limit during off-hook conditions. however, note that the ringing loop length rather than the dc loop length, will be the factor to determine operating loop length. battery reversal rate the rate of battery reverse is controlled or ramped by capacitors fb1 and fb2. table 20 below shows fb1 and fb2 values vs. typical ramp time. leave fb1 and fb2 open if it is not desired to ramp the rate of battery reversal. table 20. fb1 and fb2 values vs. typical ramp time supervision the l9216 offers the loop closure and ring trip supervi- sion functions. internal to the device, the outputs of these detectors are multiplexed into a single package output, nstat. additionally, a common-mode current detector for tip or ring ground detection is included for ground key applications. loop closure the loop closure has a fixed typical 10.5 ma on- to off- hook threshold in the active mode and a fixed 11.5 ma on- to off-hook threshold from the scan mode. in either case, there is a 2 ma hysteresis with v cc = 5 v and a 1 ma hysteresis with v cc = 3.3 v. ring trip the ring trip detector requires only a single-pole filter at the input, minimizing external components. an r/c combination of 383 k w and 0.1 m f, for a filter pole at 5.15 hz, is recommended. the ring trip threshold is internally fixed as a function of battery voltage and is given by: rt (ma) = 67 * {(0.0045 * v bat1 ) + 0.317} where: rt is ring trip current in ma. v bat1 is the magnitude of the ring battery in v. there is a 6 ma to 8 ma hysteresis. tip or ring ground detector in the ground key or ground start applications, a com- mon-mode current detector is used to indicate either a tip- or ring-ground has occurred (ground key) or an off- hook has occurred (ground start). for ground start applications detection may be seen at the output of the common mode current detector (rgdet) or the loop closure detector (nstat). if icm is used, the detection threshold is set by con- necting a resistor from icm to v cc . 205 x v cc /r icm (k w ) = i th (ma) additionally, a filter capacitor across r icm will set the time constant of the detector. no hysteresis is associ- ated with this detector. the rc filter at icm gives immunity to longitudinal currents. c fb1 and c fb2 transition time 0.01 m f 20 ms 0.1 m f 220 ms 0.22 m f 440 ms 0.47 m f 900 ms 1.0 m f 1.8 s 1.22 m f2.25 s 1.3 m f 2.5 s 1.4 m f 2.7 s 1.6 m f 3.2 s v bat2 v oh C i limit --------------------------------------
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 25 supervision (continued) tip or ring ground detector (continued) also in the ground start mode, the fixed loop current threshold associated with the nstat detector output is internally adjusted to account for common-mode cur- rent detection in ground start mode (as opposed to dif- ferential current in loop start mode) maintain the detector at 10 ma. thus, nstat may also be used for loop closure detion in ground start. however, the detec- tor at nstat is not filtered against longitudinal cur- rents, which may or may not be an issue in short loop applications. using nstat will also save components at icm. power ring the device offers a ring mode, in which a balanced power ring signal is provided to the tip/ring pair. during the ring mode, a user-supplied low-voltage ring signal is input to the devices ring in input. this signal is amplified to produce the balanced power ring signal. the user may supply a sine wave input, pwm input, or a square wave to produce sinusoidal or trapezoidal ringing at tip and ring. various crest factors are shown for illustrative pur- poses. 12-3346a (f) note: slew rate = 5.65 v/ms; trise = tfall = 23 ms; pwidth = 2 ms; period = 50 ms. figure 9. ringing waveform crest factor = 1.6 12-3347a (f) note: slew rate = 10.83 v/ms; trise = tfall = 12 ms; pwidth = 13 ms; period = 50 ms. figure 10. ringing waveform crest factor = 1.2 voltage applied to the load may be increased by using a filtered square wave input to produce a lower crest factor trapezoidal power ring signal at tip and ring. time (s) C80 C60 C40 C20 0 20 40 60 80 0.00 0.02 0.06 0.04 0.08 0.10 0.12 0.14 0.16 0.18 0.20 volts (v) time (s) C80 C60 C40 C20 0 20 40 60 80 0.00 0.02 0.06 0.04 0.08 0.10 0.12 0.14 0.16 0.18 0.20 volts (v)
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 26 agere systems inc. supervision (continued) power ring (continued) sine wave input signal and sine wave power ring signal output the low-voltage sine wave input is applied to the l9216 at pin ring in . this signal should be ac-coupled through 0.47 m f. during the ring mode, the signal at ring in is amplified and presented to the subscriber loop. the differential gain from ring in to tip and ring is a nominal 55. when the device enters the ring mode, the tip/ring overhead set at ovh and the scan clamp circuit is dis- abled, allowing the voltage magnitude of the power ring signal to be maximized. additionally, in the ring mode, the loop current limit is increased 2.5x the value set by the v prog voltage. the magnitude of the power ring voltage will be a func- tion of the gain of the ring amplifier, the high voltage battery, and the input signal at ring in . the input range of the signal at ring in is 0 v to vcc. as the input volt- age at ring in is increased, the magnitude of the power ring voltage at tip and ring will increase linearly, per the differential gain of 55, until the tip and ring drive amplifi- ers begin to saturate. once the tip and ring amplifiers reach saturation, further increases of the input signal will cause clipping distortion of the power ring signal at tip and ring. the ring signal will appear balanced on tip and ring. that is, the power ring signal is applied to both tip and ring, with the signal on tip 180 (180 degrees) out of phase from the signal on ring. figure 11 shows typical operation of the ring mode, prior to saturation of the tip and ring drive amplifiers. a C70 v battery is used with a 100 w loop and a 1 ren load. the input signal is 1 v through a 0.47 m f capaci- tor at ring in , (the input circuit is shown in figure 12). this produces a voltage swing from C34 v to C60 v on ring and from C8 v to C34 v on tip, as shown in figure 11. thus, the total voltage swing is 52 v (60 v to 8 v) for a 1 v input, which is approximately the differen- tial gain of the device. note that the tip and ring power ring signals will swing around v battery divided by two. in this case, there is a C70 v battery so tip and ring swing around C34 v. 12-3573f 12-3574f figure 11. ring mode typical operation 0 C60 0.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 0.76 0.78 time 0.80 C20 C40 vring vtip 1.0 C1.0 0.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 0.76 0.78 time 0.80 0.5 0.0 C0.5 vringin
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 27 supervision (continued) power ring (continued) sine wave input signal and sine wave power ring signal output (continued) it is recommended that the input level at ring in be adjusted so that the power ring signal at tip and ring is just at the edge or slightly clipping. this gives maximum power transfer with minimal distortion of the sine wave. the tip side will saturate at a nominal 1 v above ground. the ring side will saturate at a nominal 3 v above battery. the input circuit for a sine wave along with waveforms to illustrate the tip and ring saturation is shown in figure 12. 12-3532j figure 12. ring in operation the point at which clipping of the power ring signal begins at tip and ring is a function of the battery voltage, the input capacitor at ring in , and the input signal at ring in and vcc. typical characteristic conditions showing the onset of clipping are given below. table 21. onset of power ringing clipping v cc = 5 v, cinput = 0.47 m f table 22. onset of power ringing clipping v cc = 3.1 v, cinput = 0.47 m f input t/r v bat1 (v) vrms (mv) vrms (v) gain C70.15 891 46.88 52.62 C68.06 858 45.11 52.58 C66.00 833 43.69 52.45 C64.08 814 42.57 52.30 C62.04 789 41.21 52.23 C60.05 747 39.11 52.36 input t/r v bat1 (v) vrms (mv) vrms (v) gain C70.12 894 47.15 52.74 C68.07 855 45.11 52.76 C66.06 824 43.38 52.65 C64.01 799 41.95 52.5 C62.00 780 40.79 52.29 C60.00 749 39.09 52.19 gnd v bat pt +1 tr 27.5x ring in 0.47 m f input l9216 v tip v ring C1 3 v 100 k w 1 v v bat = C75 v 71 v
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 28 agere systems inc. supervision (continued) power ring (continued) sine wave input signal and sine wave power ring signal output (continued) during nonring modes, the sinusoidal ringing waveform may be left on at ring in . via the state table, the ring signal will be removed from tip and ring even if the low- voltage input is still present at ring in . there are certain timing considerations that should be made with respect to state changes which are detailed in the switching behavior of l9215/6 ringing slic application note. pwm input signal and sine wave power ring signal output a pulse-width modulated (pwm) signal may be used to provide the ringing input to ring in . the signal is applied through a low-pass filter and ac-coupled into ring in as shown in figure 13 below. this approach gives a sine wave output at tip and ring. 12-3578bf figure 13. l9215/16 ringing input circuit selection table for square wave and pwm inputs table 23. signal and component selection chart v bat v cc input r1 c1 c2 cf typical 5 ren ringing voltage rms 70 v 5 v 5 v square 12 k w 1 m f0.47 m f 1.3 48 v 70 v 3 v 3 v square 7 k w 1 m f0.47 m f 1.3 49 v 70 v 5 v 10 khz pwm 5 v 10 k w 0.22 m f0.47 m fsine 42 v 70 v 3 v 10 khz pwm 3 v 10 k w 0.22 m f0.47 m fsine 42 v 70 v 5 v 90 khz pwm 5 v 7 k w 0.1 m f0.47 m fsine 42 v 70 v 3 v 90 khz pwm 3 v 7 k w 0.1 m f0.47 m fsine 42 v 85 v 5 v 5 v square 10 k w 1 m f0.47 m f 1.3 59 v 85 v 3 v 3 v square 7 k w 1 m f0.47 m f 1.3 51 v 85 v 5 v 10 khz pwm 5 v 10 k w 0.22 m f0.47 m fsine 51 v 85 v 3 v 10 khz pwm 3 v 4 k w 0.22 m f0.47 m fsine 47 v 85 v 5 v 90 khz pwm 5 v 4 k w 0.1 m f0.47 m fsine 51 v 85 v 3 v 90 khz pwm 3 v 4 k w 0.1 m f0.47 m fsine 49 v input r 1 c 1 c 2 ring in l9215/16
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 29 supervision (continued) power ring (continued) pwm input signal and sine wave power ring sig- nal output (continued) modulation waveforms showing pwm are in figure 14 below. figure 14. modulation waveforms 5 v v cc operation a pwm signal was generated with an hp ? 8116 function generator modulated with a 20 hz signal. the optimal frequency used was 10 khz. the pwm signal amplitude was 5.0 v (0 v to 5 v). this signal is shown in figure 15. 12-3575f figure 15. 5 v pwm signal amplitude this input produced 44.96 vrms ringing signal on tip/ring under open-loop conditions and 42.0 vrms was delivered to 5 ren load. the ringing output on ring, with v cc = 5 v, is shown in figure 16. 1660 notes: the modulating 20 hz signal thd was measured at 1.3%. the tip/ring 20 hz signal thd was measured at 1%. v bat1 = C70.6 v, v bat2 = C26.5 v, v cc = 5.019 v. pwm input 10 khz, 5.0 vp-p. r 1 = 10 k w , c 1 = 0.22 m f, c 2 = 0.47 m f. figure 16. ringing output on ring, with v cc = 5 v 12-3381(f) a. upper = pwm signal centered at 10 khz lower = modulation signal 12-3380(f) b. same as a but expanded
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 30 agere systems inc. supervision (continued) power ring (continued) 3.3 v v cc operation a pwm signal was generated with an hp 8116 func- tion generator modulated with a 20 hz signal. the opti- mal frequency used was 10 khz. the pwm signal amplitude was 3.10 v (0 v to 3.10 v). this input signal is shown in figure 17. 12-3571f figure 17. 3.3 v pwm signal amplitude this produced 44.96 vrms ringing signal on tip/ring under open-loop conditions and 42.0 vrms was deliv- ered to 5 ren load. the ringing output on ring with v cc = 3.1 v is shown in figure 18. 1660 notes: the modulating 20 hz signal thd was measured at 1.3%. the tip/ring 20 hz signal thd was measured at 1%. v bat1 = C70.6 v, v bat2 = C26.5 v, v cc = 3.10 v. pwm input 10 khz, 3.1 vp-p. r 1 = 10 k w , c 1 = 0.22 m f, c 2 = 0.47 m f. figure 18. ringing output on ring, with v cc = 3.1 v during nonring modes, the pwm waveform may be left on at ring in . via the state table, the ring signal will be removed from tip and ring even if the low-voltage input is still present at ring in . there are certain timing con- siderations that should be made with respect to state changes which are detailed in the switching behavior of l9215/6 ringing slic application note. square wave input signal and trapezoidal power ring signal output a low-voltage square wave signal may be used to pro- vide the ringing input to ring in . the signal is applied through a low-pass filter and ac-coupled into ring in as shown in figure 13 and table 23. this approach gives a trapezoidal wave output at tip and ring. using this approach, a trapezoidal waveform can be achieved at tip and ring. this has the advantage of increasing the power transfer to the load for a given battery voltage, thus increasing the effective ringing loop length as compared to a sine wave. the actual crest factor achieved is a function of the magnitude of the battery, the magnitude of the input voltage, fre- quency, and r 1 . 12-3572f notes: ch1cmos input (5 v) at ring in . ch2filtered input at ring in . ch3tip. ch4ring. r 1 = 14 k w , c 1 = 1.0 m f, c 2 = 0.47 m f. v bat1 = C70 v, vrms = 51 v, v p-p = 67 v, frequency = 20 hz, crest factor = 1.3. figure 19. square wave input signal and trapezoi- dal power ring signal output ch1 ch2 ch3 ch4
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 31 supervision (continued) power ring (continued) square wave input signal and trapezoidal power ring signal output (continued) figure 20 and figure 21 provide some guidance to the relationship between crest factor, battery voltage, and r 1 value. 12-3576f figure 20. crest factor vs. battery voltage 12-3577f figure 21. crest factor vs. r (k w ) during nonring modes, the square wave input may be left on or removed from ring in . via the state table, the ring signal will be removed from tip and ring even if the low-voltage input is still present at ring in . however, removing the waveform has certain advantages in terms of the timing of state. these advantages are detailed in the switch- ing behavior of l9215/16 ringing slic application note. 1.36 58 bat v cf 60 62 64 66 68 70 72 1.35 1.34 1.33 1.32 1.31 1.3 1.29 1.28 1.27 1.26 1.5 1.45 10 r (k w) cf 1.4 1.35 1.3 1.25 10.5 11 11.5 12 12.5 13 13.5 14
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 32 agere systems inc. ac applications ac parameters there are four key ac design parameters. termination impedance is the impedance looking into the 2-wire port of the line card. it is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. transmit gain is measured from the 2-wire port to the pcm highway, while receive gain is done from the pcm highway to the transmit port. transmit and receive gains may be specified in terms of an actual gain, or in terms of a transmission level point (tlp), that is the actual ac transmission level in dbm. finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. codec types at this point in the design, the codec needs to be selected. the interface network between the slic and codec can then be designed. below is a brief codec feature summary. first-generation codecs these perform the basic filtering, a/d (transmit), d/a (receive), and m -law/a-law companding. they all have an op amp in front of the a/d converter for transmit gain setting and hybrid balance (cancellation at the summing node). depending on the type, some have differential analog input stages, differential analog out- put stages, 5 v only or 5 v operation, and m -law/a-law selectability. these are available in single and quad designs. this type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. an example of this type of codec is the agere t7504 quad 5 v only codec. this type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. further ac parameters are fixed by the external r/c network so software control of ac parameters is diffi- cult. third-generation codecs this class of devices includes all ac parameters set digitally under microprocessor control. depending on the device, it may or may not have data control latches. additional functionality sometimes offered includes tone plant generation and reception, ppm generation, test algorithms, and echo cancellation. again, this type of codec may be 3.3 v, 5 v only, or 5 v operation, sin- gle quad or multichannel, and m -law/a-law or 16-bit lin- ear coding selectable. examples of this type of codec are the agere t8535/6 (5 v only, quad, standard fea- tures), t8537/8 (3.3 v only, quad, standard features), t8533/4 (5 v only, quad with echo cancellation), and the t8531/32 (5 v only multichannel). ac interface network the ac interface network between the l9216 and the codec will vary depending on the codec selected. with a first-generation codec, the interface between the l9216 and codec actually sets the ac parameters. with a third-generation codec, all ac parameters are set dig- itally, internal to the codec; thus, the interface between the l9216 and this type of codec is designed to avoid overload at the codec input in the transmit direction and to optimize signal to noise ratio (s/n) in the receive direction. because the design requirements are very different with a first- or third-generation codec, the l9216 is offered with two different receive gains. each receive gain was chosen to optimize, in terms of external com- ponents required, the ac interface between the l9216 and codec.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 33 ac applications (continued) ac interface network (continued) with a first-generation codec, the termination imped- ance is set by providing gain shaping through a feed- back network from the slic vitr output to the slic rcvn/rcvp inputs. the l9216 provides a transcon- ductance from t/r to vitr in the transmit direction and a single-ended to differential gain from either rcvn or rcvp to t/r in the receive direction. assuming a short from vitr to rcvn or rcvp, the maximum imped- ance that is seen looking into the slic is the product of the slic transconductance multiplied by the slic receive gain, plus the protection resistors. the various specified termination impedances can range over the voiceband as low as 300 w up to over 1000 w . thus, if the slic gains are too low, it will be impossible to syn- thesize the higher termination impedances. further, the termination that is achieved will be far less than what is calculated by assuming a short for slic output to slic input. in the receive direction, in order to control echo, the gain is typically a loss, which requires a loss net- work at the slic rcvn/rcvp inputs, which will reduce the amount of gain that is available for termina- tion impedance. for this reason, a high-gain slic is required with a first-generation codec. with a third-generation codec, the line card designer has different concerns. to design the ac interface, the designer must first decide upon all termination imped- ance, hybrid balances, and transmission level point (tlp) requirements that the line card must meet. in the transmit direction, the only concern is that the slic does not provide a signal that is too hot and overloads the codec input. thus, for the highest tlp that is being designed to, given the slic gain, the designer, as a function of voiceband frequency, must ensure the codec is not overloaded. with a given tlp and a given slic gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resis- tor divider, between the slic output and codec input. note also that some third-generation codecs require the designer to provide an inherent resistive termina- tion via external networks. the codec will then provide gain shaping, as a function of frequency, to meet the return loss requirements. this feedback will increase the signal at the codec input and increase the likeli- hood that a resistor divider is needed in the transmit direction. further stability issues may add external components or excessive ground plane requirements to the design. in the receive direction, the issue is to optimize the s/n. again, the designer must consider all the consid- ered tlps. the idea, for all desired tlps, is to run the codec at or as close as possible to its maximum output signal, to optimize the s/n. remember, noise floor is constant, so the hotter the signal from the codec, the better the s/n. the problem is if the codec is feeding a high gain slic, either an external resistor divider is needed to knock the gain down to meet the tlp requirements, or the codec is not operated near maxi- mum signal levels, thus compromising the s/n. thus, it appears that the solution is to have a slic with a low gain, especially in the receive direction. this will allow the codec to operate near its maximum output signal (to optimize s/n), without an external resistor divider (to minimize cost). to meet the unique requirements of both types of codecs, the l9216 offers two receive gain choices. these receive gains are mask-programmable at the factory and are offered as two different code variations. for interface with a first-generation codec, the l9216 is offered with a receive gain of 8. for interface with a third-generation codec, the l9216 is offered with a receive gain of 2. in either case, the transconductance in the transmit direction or the transmit gain is 300 w . these receive gain options afford the designer the flex- ibility to maximize performance and minimize external components, regardless of the type of codec chosen.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 34 agere systems inc. ac applications (continued) design examples first-generation codec ac interface network resistive termination the reference circuit in figure 23 shows the complete slic schematic for interface to the agere t7504 first- generation codec for a resistive termination imped- ance. for this example, the ac interface was designed for a 600 w resistive termination and hybrid balance with transmit gain and receive gain set to 0 dbm. this is a lower feature application example and uses single battery operation, fixed overhead, current limit, and loop closure threshold. resistor r gn is optional. it compensates for any mis- match of input bias voltage at the rcvn/rcvp inputs. if it is not used, there may be a slight offset at tip and ring due to mismatch of input bias voltage at the rcvn/rcvp inputs. it is very common to simply tie rcvn directly to ground in this particular mode of oper- ation. if used, to calculate rgn, the impedance from rcvn to ac ground should equal the impedance from rcvp to ac ground. example 1, real termination the following design equations refer to the circuit in figure 22. use these to synthesize real termination impedance. termination impedance: z t = receive gain: transmit gain: hybrid balance: h bal = 20log h bal = 20log to optimize the hybrid balance, the sum of the currents at the vfx input of the codec op amp should be set to 0. the expression for zhb becomes the following: v t/r i t/r C ------------ z t 50 w 2 + r p 2400 1 r t1 r gp -------- - r t1 r rcv ----------- - ++ ----------------------------------- + = g rcv v t/r v fr ----------- - = g rcv 8 1 r rcv r t1 ----------- r rcv r gp ----------- - ++ ? ?? 1 z t z t/r -------- - + ? ?? ------------------------------------------------------------------ = g tx v gsx v t/r ---------- - = g tx r x C r t2 --------- 300 z t/r -------- - = r x r hb ----------- - g tx C g rcv ? ?? v gsx v fr -------------- - ? ?? r hb k w () r x g tx g rcv ------------------- =
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 35 ac applications (continued) design examples (continued) example 1, real termination (continued) 0586 (f) figure 22. ac equivalent circuit figure 23. agere t7504 first-generation codec resistive termination r p z t + C r p v t/r i t/r v s z t/r + C ring a v = C1 a v = 1 vitr current sense tip + C r t1 r rcv r hb1 r t2 rcvn rcvp r x vgsx vf x in v fr 1/4 t7504 codec r gp +2.4 v C0.300 v/ma a v = 4 l9216 vf x ip 18 w 18 w + C + C v bat1 bgnd v bat2 v cc agnd icm rgdet c bat1 0.1 m f c bat2 0.1 m f c cc 0.1 m f rtflt dcout pr pt v ref c rt 0.1 m f r rt 383 k w agere l7591 v bat1 fusible or ptc 30 w 30 w cf1 cf2 rate of battery reversal not ramped fb1 fb2 nstatb2b1b0 c f1 0.22 m f c f2 0.1 m f ring in vitr rcvp rcvn itr vtx txi r gx 4750 w v bat1 d bat1 v bat2 v cc c tx 0.1 m f c 2 0.47 m f 1/4 t7504 codec r t6 c c1 r x gsx +2.4 v r hb1 vfxin r rcv r t3 r gp c c2 v fro dx dr fse fsep mclk asel control inputs sync and pcm highway clock r n2 C + 49.9 k w 100 k w 100 k w 60.4 k w 0.1 m f 17.65 k w 26.7 k w 69.8 k w 0.1 f L9216A fusible or ptc v prog v ref v ref r 1 12 k w c 1 1.0 m f
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 36 agere systems inc. ac applications (continued) design examples (continued) example 1, real termination (continued) table 24. parts list l9216; agere t7504 first-generation codec resistive termination; nonmeter pulse application notes: termination impedance = 600 w . hybrid balance = 600 w . tx = 0 dbm. rx = 0 dbm. name value tolerance rating function fault protection r pt 30 w 1% fusible or ptc protection resistor. r pr 30 w 1% fusible or ptc protection resistor. protector agere l7591 secondary protection. power supply c bat1 0.1 m f 20% 100 v v bat filter capacitor. c bat2 0.1 m f 20% 50 v v bat filter capacitor. |v bat2 | < |v bat1 |. d bat1 1n4004 reverse current. c cc 0.1 m f 20% 10 v v cc filter capacitor. c f1 0.22 m f 20% 100 v filter capacitor. c f2 0.1 m f 20% 100 v filter capacitor. ring/ring trip c 1 1.0 m f 20% 10 v ring filter for square wave. c 2 0.47 m f 20% 10 v ac-couple input ring signal. r 1 12 k w 1% 1/16 w ring filter for square wave. c rt 0.1 m f 20% 10 v ring trip filter capacitor. r rt 383 k w 1% 1/16 w ring trip filter resistor. ac interface r gx 4750 w 1% 1/16 w sets t/r to vitr transconductance. c tx 0.1 m f 20% 10 v ac/dc separation. c c1 0.1 m f 20% 10 v dc blocking capacitor. c c2 0.1 m f 20% 10 v dc blocking capacitor. r t3 69.8 k w 1% 1/16 w with r gp and r rcv , sets termination impedance and receive gain. r t6 49.9 k w 1% 1/16 w with r x , sets transmit gain. r x 100 k w 1% 1/16 w with r t6 , sets transmit gain. r hb1 100 k w 1% 1/16 w with r x , sets hybrid balance. r rcv 60.4 k w 1% 1/16 w with r gp and r t3 , sets termination impedance and receive gain. r gp 26.7 k w 1% 1/16 w with r rcv and r t3 , sets termination impedance and receive gain. r gn optional 17.6 k w 1% 1/16 w optional. compensates for input offset at rcvn/rcvp.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 37 ac applications (continued) design examples (continued) first-generation codec ac interface network complex termination the reference circuit in figure 26 shows the complete slic schematic for interface to the agere t7504 first- generation codec for the german complex termination impedance. for this example, the ac interface was designed for a 220 w + (820 w || 115 nf) complex termination and hybrid balance with transmit gain and receive gain set to 0 dbm. for illustration purposes, 1 vrms ppm injection was assumed in this example. this implies the overhead voltage is increased to 7.24 v and no meter pulse rejection is required. also, this example illustrates the device using fixed overhead and current limit. complex termination impedance design example the gain shaping necessary for a complex termination impedance may be done by shaping across the ax amplifier at nodes itr and vtx. complex termination is specified in the form: 5-6396(f) to work with this application, convert termination to the form: 5-6398(f) where: r 1 = r 1 + r 2 r 2 = (r 1 + r 2 ) c = c ac interface using first-generation codec r gx /r tgs /c gs (z tg ): these components give gain shap- ing to get good gain flatness. these components are a scaled version of the specified complex termination impedance. note for pure (600 w ) resistive terminations, compo- nents r tgs and c gs are not used. resistor r gx is used and is still 4750 w . r x /r t6 : with other components set, the transmit gain (for complex and resistive terminations) r x and r t6 are varied to give specified transmit gain. r t3 /r rcv /r gp : for both complex and resistive termina- tions, the ratio of these resistors sets the receive gain. for resistive terminations, the ratio of these resistors sets the return loss characteristic. for complex termi- nations, the ratio of these resistors sets the low-fre- quency return loss characteristic. c n /r n1 /r n2 : for complex terminations, these compo- nents provide high-frequency compensation to the return loss characteristic. for resistive terminations, these components are not used and rcvn is connected to ground via a resistor. r hb : sets hybrid balance for all terminations. set z tg gain shaping: z tg = r gx || r tgs + c gs which is a scaled version of z t/r (the specified termination resistance) in the r 1 || r 2 + c form. r gx must be 4750 w to set slic transconductance to 300 v/a. r gx = 4750 w at dc, c gs and c are open. r gx = m x r 1 where m is the scale factor. m = it can be shown: r tgs = m x r 2 and c tgs = r 2 c r 1 r 1 c r 2 r 1 r 2 ------- r 2 r 1 r 2 + --------------------- ? ?? 2 4750 r 1 -------------- c m ------
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 38 agere systems inc. ac applications (continued) design examples (continued) transmit gain transmit gain will be specified as a gain from t/r to pcm, t x (db). since pcm is referenced to 600 w and assumed to be 0 db, and in the case of t/r being refer- enced to some complex impedance other than 600 w resistive, the effects of the impedance transformation must be taken into account. again, specified complex termination impedance at t/r is of the form: 5-6396(f) first, calculate the equivalent resistance of this network at the midband frequency of 1000 hz. r eq = using r eq , calculate the desired transmit gain, taking into account the impedance transformation: t x (db) = t x (specified[db]) + 20log t x (specified[db]) is the specified transmit gain. 600 w is the impedance at the pcm, and r eq is the impedance at tip and ring. 20log represents the power loss/gain due to the impedance transformation. note that in the case of a 600 w pure resistive termina- tion at t/r 20log = 20log = 0. thus, there is no power loss/gain due to impedance transformation and t x (db) = t x (specified[db]) . finally, convert t x (db) to a ratio, g tx : t x (db) = 20log g tx the ratio of r x /r t6 is used to set the transmit gain: = g tx ? ? with a quad agere codec such as t7504: r x < 200 k w r 2 c r 1 2 p f () 2 c 1 2 r 1 r 2 2 r 1 r 2 ++ 12 p f () 2 r 2 2 c 1 2 + ----------------------------------------------------------------------------- ? ?? 2 2 p f r 2 2 c 1 12 p f () 2 r 2 2 c 1 2 + -------------------------------------------------- - ? ?? 2 + 600 r eq ---------- - 600 r eq ---------- - 600 r eq ---------- - 600 600 --------- - r x r t6 ---------- 318.25 20 ----------------- - 1 m ---- - 5-6400.p (f) figure 24. interface circuit using first-generation codec (blocking capacitors not shown) 0.1 m f r tgs v tx r gx = 4750 w t xi v itr r t6 r x r t3 r hb codec output drive amp codec op amp C + 20 c n r n1 r n2 r gp r rcv Ci t/r 318.25 c gs rcvn rcvp
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 39 ac applications (continued) design examples (continued) receive gain ratios of r rcv , r t3 , r gp will set both the low-frequency termination and receive gain for the complex case. in the complex case, additional high-frequency compen- sation, via c n , r n1 , and r n2 , is needed for the return loss characteristic. for resistive termination, c n , r n1 , and r n2 are not used and rcvn is tied to ground via a resistor. determine the receive gain, g rcv , taking into account the impedance transformation in a manner similar to transmit gain. r x (db) = r x (specified[db]) + 20log r x (db) = 20log g rcv then: g rcv = and low-frequency termination z ter(low) = + 2r p + 50 w z ter(low) is the specified termination impedance assum- ing low frequency (c or c is open). r p is the series protection resistor. 50 w is the typical internal feed resistance. these two equations are best solved using a computer spreadsheet. next, solve for the high-frequency return loss compen- sation circuit, c n , r n1 , and r n2 : c n r n2 = c g r tgp r n1 = r n2 there is an input offset voltage associated with nodes rcvn and rcvp. to minimize the effect of mismatch of this voltage at t/r, the equivalent resistance to ac ground at rcvn should be approximately equal to that at rcvp. refer to figure 25 (with dc blocking capaci- tors). to meet this requirement, r n2 = r gp || r t3 . hybrid balance set the hybrid cancellation via r hb . r hb = if a 5 v only codec such as the agere t7504 is used, dc blocking capacitors must be added as shown in figure 25. this is because the codec is referenced to 2.5 v and the slic to groundwith the ac coupling, a dc bias at t/r is eliminated and power associated with this bias is not consumed. typically, values of 0.1 f to 0.47 f capacitors are used for dc blocking. the addition of blocking capaci- tors will cause a shift in the return loss and hybrid bal- ance frequency response toward higher frequencies, degrading the lower-frequency response. the lower the value of the blocking capacitor, the more pro- nounced the effect is, but the cost of the capacitor is lower. it may be necessary to scale resistor values higher to compensate for the low-frequency response. this effect is best evaluated via simulation. a pspice ? model for the l9216 is available. design equation calculations seldom yield standard component values. conversion from the calculated value to standard value may have an effect on the ac parameters. this effect should be evaluated and opti- mized via simulation. r eq 600 ---------- - 4 1 r rcv r t3 --------------- r rcv r gp --------------- ++ ----------------------------------------------- - 2400 1 r t3 r gp ----------- - r t3 r rcv --------------- ++ -------------------------------------------- 2r p 2400 ------------ - 2400 2r p ------------ - r tgs r tgp ------------- - ? ?? 1 C r x g rcv g tx ------------------------------ -
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 40 agere systems inc. ac applications (continued) design examples (continued) blocking capacitors 5-6401.m (f) figure 25. ac interface using first-generation codec (including blocking capacitors) for complex termi- nation impedance figure 26. agere t7504 first-generation codec complex termination 0.1 m f r tgs vtx r gx = 4750 w txi vitr r t6 r x r t3 r hb codec output drive amp codec op amp C + 20 c n r n1 r n2 r gp r rcv Ci t/r 318.25 c gs c b1 2.5 v c b2 rcvn rcvp v bat1 bgnd v bat2 v cc agnd icm rgdet ground key not used c bat1 0.1 m f c bat2 0.1 m f c cc 0.1 m f rtflt dcout pr pt c rt 0.1 m f r rt 383 k w agere l7591 v bat1 fusible 30 w rate of battery reversal not ramped vitr rcvp rcvn itr vtx txi r gx 4750 w r tgs 1.74 k w c gs 12 nf v bat1 d bat1 v bat2 v cc c tx 0.1 m f r t6 r hb1 r t3 r rcv c n r gp r n2 30 w c c2 L9216A c c1 cf1 cf2 fb1 fb2 nstat b2 b1 b0 c f1 0.22 m f c f2 0.1 m f ring in c ring 0.47 m f from/to control ring fusible 47.5 k w 54.9 k w 127 r n1 k w 59.0 k w 49.9 k w 113 k w 120 pf 0.1 m f 0.1 m f 40.6 k w v ref or ptc or ptc r x vfxin dx +2.4 C + gsx vfro 1/4 t7504 codec pcm highwa y sync and clock contro l inputs dr fse fsep mclk asel v prog v ref v ref 115 k w
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 41 ac applications (continued) design examples (continued) blocking capacitors (continued) table 25. parts list l9216; agere t7504 first-generation codec complex termination; meter pulse application termination impedance = 220 w + (820 w || 115 nf), hybrid balance = 220 w + (820 w || 115 nf) tx = 0 dbm, rx = 0 dbm. name value tolerance rating function fault protection r pt 30 w 1% fusible or ptc protection resistor. r pr 30 w 1% fusible or ptc protection resistor. protector agere l7591 secondary protection. power supply c bat1 0.1 m f 20% 100 v v bat filter capacitor. c bat2 0.1 m f 20% 50 v v bat filter capacitor. |v bat2 | < |v bat1 |. d bat1 1n4004 reverse current. c cc 0.1 m f 20% 10 v v cc filter capacitor. c f1 0.22 m f 20% 100 v filter capacitor. c f2 0.1 m f 20% 100 v filter capacitor. ring/ring trip c ring 0.47 m f 20% 10 v ac-couple input ring signal. c rt 0.1 m f 20% 10 v ring trip filter capacitor. r rt 383 k w 1% 1/16 w ring trip filter resistor. ac interface r gx 4750 w 1% 1/16 w sets t/r to vitr transconductance. r tgs 1.74 k w 1% 1/16 w gain shaping for complex termination. c gs 12 nf 5% 10 v gain shaping for complex termination. c tx 0.1 m f 20% 10 v ac/dc separation. c c1 0.1 m f 20% 10 v dc blocking capacitor. c c2 0.1 m f 20% 10 v dc blocking capacitor. r t3 49.9 k w 1% 1/16 w with r gp and r rcv , sets termination impedance and receive gain. r t6 40.2 k w 1% 1/16 w with r x , sets transmit gain. r x 115 k w 1% 1/16 w with r t6 , sets transmit gain. r hb1 113 k w 1% 1/16 w with r x , sets hybrid balance. r rcv 59.0 k w 1% 1/16 w with r gp and r t3 , sets termination impedance and receive gain. r gp 54.9 k w 1% 1/16 w with r rcv and r t3 , sets termination impedance and receive gain. c n 120 pf 20% 10 v high frequency compensation. r n1 127 k w 1% 1/16 w high frequency compensation. r n2 47.5 k w 1% 1/16 w high frequency compensation, compensate for dc offset at rcvp/rcvn.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 42 agere systems inc. ac applications (continued) design examples (continued) third-generation codec ac interface networkcomplex termination the following reference circuit, figure 27, shows the complete slic schematic for interface to the agere t8536 third-generation codec. all ac parameters are programmed by the t8536. note this codec differentiates itself in that no external components are required in the ac interface to provide a dc termination impedance or for stability. for illustration purposes, 0.5 vrms ppm injection was assumed in this example and no meter pulse rejection is used. also, this example illustrates the device using programmable overhead and current limit. please see the t8535/6 data sheet for information on coefficient programming. figure 27. third-generation codec ac interface network; complex termination v bat1 bgnd v bat2 v cc agnd icm rgdet ground key not used c bat1 0.1 m f c bat2 0.1 m f c cc 0.1 m f rtflt dcout pr pt v prog v ref c rt 0.1 m f r rt 383 k w agere l7591 v bat1 fusible or ptc 50 w 50 w cf1 cf2 rate of battery reversal not ramped fb1 fb2 nstat b2 b1 b0 c f1 0.22 m f c f2 0.1 m f ring in vitr rcvp rcvn itr vtx txi r gx 4750 w v bat1 d bat1 v bat2 v cc c tx 0.1 m f c ring 0.47 m f c c1 pcm highway dx0 dr0 dx1 dr1 fs bclk dgnd v dd sync and v dd vfxi vfrop vfron slic4a slic3a slic2a slic0a clock l9216g from/to control b2 b1 nstat b0 0.1 m f fusible or ptc r cin 20 m w 1/4 t8536/8
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 43 ac applications (continued) design examples (continued) third-generation codec ac interface networkcomplex termination (continued) table 26. parts list l9216; agere t8536 third-generation codec ac and dc parameters; fully programmable * for loop stability, increase to 50 w minimum if synthesizing 900 w or 900 w + 2.16 m f termination impedance. name value tolerance rating function fault protection r pt 50 w 1% fusible or ptc protection resistor*. r pr 50 w 1% fusible or ptc protection resistor*. protector agere l7591 secondary protection. power supply c bat1 0.1 m f 20% 100 v v bat filter capacitor. c bat2 0.1 m f 20% 50 v v bat filter capacitor. |v bat2 | < |v bat1 |. d bat1 1n4004 reverse current. c cc 0.1 m f 20% 10 v v cc filter capacitor. c f1 0.22 m f 20% 100 v filter capacitor. c f2 0.1 m f 20% 100 v filter capacitor. ring/ring trip c ring 0.47 m f 20% 10 v ac-couple input ring signal. c rt 0.1 m f 20% 10 v ring trip filter capacitor. r rt 383 k w 1% 1/16 w ring trip filter resistor. ac interface r gx 4750 w 1% 1/16 w sets t/r to vitr transconductance. r cin 20 m w 5% 1/16 w dc bias. c tx 0.1 m f 20% 10 v ac/dc separation. c c1 0.1 m f 20% 10 v dc blocking capacitor.
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 44 agere systems inc. outline diagrams 28-pin plcc dimensions are in millimeters. note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schemat- ics to assist your design efforts, please contact your agere sales representative. 5-2506r.8(f) 1.27 typ 0.330/0.533 0.10 seating plane 0.51 min typ 4.572 max 12 18 11 5 4126 25 19 12.446 0.127 pin #1 identifier zone 11.506 0.076 11.506 0.076 12.446 0.127
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 45 outline diagrams (continued) 48-pin mlcc dimensions are in millimeters. notes: the dimensions in this outline diagram are intended for informational purposes only. for detailed schemat- ics to assist your design efforts, please contact your agere sales representative. the exposed pad on the bottom of the package will be at v bat1 potential. 0195mod pin #1 identifier zone 1 7.00 6.75 seating plane 0.08 0.65/0.80 0.20 ref detail a 7.00 5.10 0.15 3 3.50 3.375 6.75 0.00/0.05 section cCc 11 spaces @ 0.50 = 5.50 0.50 bsc 0.18/0.30 0.30/0.45 0.01/0.05 1.00 max 12 0.18/0.30 0.24/0.60 0.24/0.60 2 1 3 2 0.50 bsc detail a cc view for even terminal/side c l exposed pad
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g 46 agere systems inc. outline diagrams (continued) 48-pin mlcc, jedec mo-220 vkkd-2 dimensions are in millimeters. notes: the dimensions in this outline diagram are intended for informational purposes only. for detailed schemat- ics to assist your design efforts, please contact your agere sales representative. the exposed pad on the bottom of the package will be at v bat1 potential. 0195a index area 7.00 3.50 seating plane 0.08 0.20 ref detail a 7.00 5.00/5.25 3.50 11 spaces @ 0.50 = 5.50 0.50 bsc 0.18/0.30 0.02/0.05 1.00 max 0.23 0.30/0.50 1 3 2 (7.00/2 x 7.00/2) pin #1 identifier zone top view side view detail b 0.23 0.18 0.18 bottom view 2.50/2.625 exposed pad detail b 0.50 bsc detail a view for even terminal/side c l
preliminary data sheet september 2001 short-loop ringing slic with ground start L9216A/g agere systems inc. 47 ordering information device part no. description package comcode lucL9216Agf-d slic gain = 8 28-pin plcc dry-bagged 108876723 lucL9216Agf-dt slic gain = 8 28-pin plcc tape & reel, dry-bagged 108876731 lucl9216ggf-d slic gain = 2 28-pin plcc tape & reel 108876780 lucl9216ggf-dt slic gain = 2 28-pin plcc tape & reel, dry-bagged 108876798 lucL9216Arg-d slic gain = 8 48-pin mlcc dry-bagged 108955477 lucl9216grg-d slic gain = 2 48-pin mlcc dry-bagged 108955469
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. copyright ? 2001 agere systems inc. all rights reserved september 2001 ds01-301alc (replaces ds00-133alc) for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 10-6522-5566 (beijing), (86) 755-695-7224 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045 ieee is a registered trademark of the institute of electrical and electronics engineers, inc. pspice is a registered trademark of microsim corporation. telcordia technologies is a trademark of bell communications research, inc. hp is a trademark of hewlett-packard company.

▲Up To Search▲

Price & Availability of L9216A

	To Download L9216A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .